How Meridian Autonomy compressed chip selection from 14 weeks to 9 days

Meridian Autonomy ships a four-tier highway autonomy stack: a passenger car, a commercial van, a heavy-duty truck cab, and a low-cost retrofit kit. Each tier targets different silicon — Jetson AGX Orin on the high end, QCS8550 in the middle, Hailo-10H plus an SoC on the retrofit. Until last year, validating that the same six perception models ran inside budget on each of those four tiers took fourteen weeks per cycle. They run that cycle twice a year. That's more than half the engineering year burned on what is, fundamentally, a measurement problem.

Meridian Autonomy ships a four-tier highway autonomy stack: a passenger car, a commercial van, a heavy-duty truck cab, and a low-cost retrofit kit. Each tier targets different silicon — Jetson AGX Orin on the high end, QCS8550 in the middle, Hailo-10H plus an SoC on the retrofit. Until last year, validating that the same six perception models ran inside budget on each of those four tiers took fourteen weeks per cycle.

The bottleneck wasn't compilation. The team had a working internal toolchain for each silicon family — they could turn an ONNX into a HEF, a TRT engine, or a QNN binary in a few hours. The bottleneck was measurement. Each new model variant needed to be characterized end-to-end on each chip, in matched-pair conditions, with a downstream consumer attached and a real input pipeline. Six models × four chips × two cycles per year is a 48-row instrumentation problem, and it was eating most of the perception team's calendar.

We started working with Meridian under the design-partner program in early 2027. The first thing we did was a measurement audit: where exactly were those fourteen weeks going? Not surprising in retrospect — most of it was spent re-instrumenting downstream consumers between model versions, then waiting on the in-house HIL rig in Munich to free up. The compiler work was a tiny fraction of the total cycle.

The intervention was twofold. First, the Meridian models moved into a private Fo'c'sle registry with cross-chip benchmark coverage attached. Every commit triggers a benchmark refresh against all four target chips, in matched-pair conditions, in our Munich lab. Engineers see the regression on the same PR. Second, the HIL sim work — which Meridian had been doing manually — moved into queued runs against scenario presets. The same six perception models now have HIL traces on highway-cut-in, urban-night, and lane-merge scenarios on every supported chip, refreshed nightly.

Cycle time fell from fourteen weeks to nine days. Half of that compression is straight measurement throughput; the other half is that engineers stopped having to context-switch between model authoring and instrumentation. The team now runs two full chip-selection cycles per quarter instead of one per half. They also now publish a public version of those benchmarks under Apache-2.0, which is how you came to find them on this site.