FastSAM-Edge

13%

YOLO-backbone segment-anything variant. Where industrial inspection lives now.

SegmentationApache-2.0INT8FP16samindustrialreal-time

138K downloads 6.8K deploymentsUpdated Mar 28, 2028

Headline:18.6ms · Hailo-8 · INT8

Overview Benchmarks4 Sim Results Deploy6 Files Discussion23

Cross-chip benchmark matrix

Every supported chip, in matched-pair runs from the Fo’c’sle HIL lab. Sortable by any column — click a header. Cells where the chip can’t run this model show Not supported.

Chip platform	Quant	Latency p50(ms)	Latency p95(ms)	Throughput	Acc. retention(%)	Power(W)	Memory(MB)	Tested by
Q Qualcomm QCS8550 48 TOPS · SoC	INT8	8.58	11.3	117 FPS	98.0	12.7	13	Publisher
H Hailo-10H 40 TOPS · M.2	INT8	9.49	11.6	105 FPS	98.6	3.2	13	Publisher
N NVIDIA Jetson Orin Nano 40 TOPS · SoM	INT8	10.5	13.2	95 FPS	99.0	14.4	13	Fo’c’sle HIL
A Ambarella CV72 32 TOPS · SoC	INT8	13.5	16.9	74 FPS	98.0	5.6	13	Fo’c’sle HIL
H Hailo-8 26 TOPS · M.2	In progress
π Raspberry Pi 5 + Hailo HAT 26 TOPS · HAT	In progress
Q Qualcomm QCS6490 12 TOPS · SoC	Not supported
Q Snapdragon 8 Gen 3 NPU 45 TOPS · SoC	Not supported
N NVIDIA Jetson AGX Orin 275 TOPS · Module	Not supported
N NVIDIA Jetson Thor 2070 TOPS · Module	Not supported
A Ambarella CV5 16 TOPS · SoC	Not supported
M MediaTek Genio 700 4 TOPS · SoC	Not supported
G Google Coral Edge TPU 4 TOPS · USB	Not supported
I Intel Movidius Myriad X 4 TOPS · SoC	Not supported
A AMD Versal AI Edge VE2302 22 TOPS · SoC	Not supported
Apple Neural Engine (M4) 38 TOPS · SoC	Not supported
R Rockchip RK3588 6 TOPS · SoC	Not supported

Leader per columnHIL conditions per row

HIL conditions

All numbers measured on Fo’c’sle HIL rigs in Tel Aviv (primary), Munich (secondary), and Pittsburgh (robotics). Single-stream, batch-1, real preprocessing, real downstream consumer. p50/p95 are over 10,000-frame steady-state windows after a 30-second warm-up. Power draw is package power, not wall power. Memory footprint is the resident model + activations footprint at peak — not on-disk.

Submitted publisher numbers are accepted only if they reproduce within ±8% of an HIL-lab matched run on the same chip in the same input mode. Otherwise they live separately under the Discussion tab.