
DINO-v3-Distilled
21%Distilled DINO-v3 backbone for downstream perception. The encoder under most of our reference models.
Cross-chip benchmark matrix
Every supported chip, in matched-pair runs from the Fo’c’sle HIL lab. Sortable by any column — click a header. Cells where the chip can’t run this model show Not supported.
| Chip platform | Quant | Latency p50(ms) | Latency p95(ms) | Throughput | Acc. retention(%) | Power(W) | Memory(MB) | Tested by |
|---|---|---|---|---|---|---|---|---|
N NVIDIA Jetson Thor 2070 TOPS · Module | FP16 | 18.2 | 23.7 | 55 FPS | 99.8 | 122.3 | 204 | Fo’c’sle HIL |
N NVIDIA Jetson AGX Orin 275 TOPS · Module | FP16 | 26.1 | 33.6 | 38 FPS | 99.7 | 55.4 | 204 | Fo’c’sle HIL |
Q Snapdragon 8 Gen 3 NPU 45 TOPS · SoC | INT8 | 38.2 | 45.8 | 26 FPS | 98.4 | 6.4 | 102 | Fo’c’sle HIL |
Q Qualcomm QCS8550 48 TOPS · SoC | INT8 | 53.4 | 64.0 | 19 FPS | 98.5 | 14.1 | 102 | Fo’c’sle HIL |
N NVIDIA Jetson Orin Nano 40 TOPS · SoM | INT8 | 63.6 | 80.3 | 16 FPS | 97.4 | 12.6 | 102 | Fo’c’sle HIL |
Apple Neural Engine (M4) 38 TOPS · SoC | FP16 | 78.1 | 99.5 | 13 FPS | 99.8 | 7.1 | 204 | Fo’c’sle HIL |
H Hailo-8 26 TOPS · M.2 | Not supported | |||||||
H Hailo-10H 40 TOPS · M.2 | Not supported | |||||||
Q Qualcomm QCS6490 12 TOPS · SoC | Not supported | |||||||
π Raspberry Pi 5 + Hailo HAT 26 TOPS · HAT | Not supported | |||||||
A Ambarella CV5 16 TOPS · SoC | Not supported | |||||||
A Ambarella CV72 32 TOPS · SoC | Not supported | |||||||
M MediaTek Genio 700 4 TOPS · SoC | Not supported | |||||||
G Google Coral Edge TPU 4 TOPS · USB | Not supported | |||||||
I Intel Movidius Myriad X 4 TOPS · SoC | Not supported | |||||||
A AMD Versal AI Edge VE2302 22 TOPS · SoC | Not supported | |||||||
R Rockchip RK3588 6 TOPS · SoC | Not supported | |||||||
HIL conditions
All numbers measured on Fo’c’sle HIL rigs in Tel Aviv (primary), Munich (secondary), and Pittsburgh (robotics). Single-stream, batch-1, real preprocessing, real downstream consumer. p50/p95 are over 10,000-frame steady-state windows after a 30-second warm-up. Power draw is package power, not wall power. Memory footprint is the resident model + activations footprint at peak — not on-disk.
Submitted publisher numbers are accepted only if they reproduce within ±8% of an HIL-lab matched run on the same chip in the same input mode. Otherwise they live separately under the Discussion tab.