FocsleFo’c’sle
MA

Meridian LanePolicy-Mini

18%
by Meridian Autonomy

Smaller lane-change policy distilled from the Meridian Tier-1 stack. Validated for cut-in, merge, and yield in HIL.

Vision-Language-ActionCustomMIXEDavlane-changepolicy
4.8K downloads 320 deploymentsUpdated Apr 8, 2028
Headline:18.2ms · NVIDIA Jetson Thor · MIXED
OverviewBenchmarks2Sim ResultsDeploy2FilesDiscussion23

Cross-chip benchmark matrix

Every supported chip, in matched-pair runs from the Fo’c’sle HIL lab. Sortable by any column — click a header. Cells where the chip can’t run this model show Not supported.

Chip platformQuantLatency p50(ms)Latency p95(ms)ThroughputAcc. retention(%)Power(W)Memory(MB)Tested by
N
NVIDIA Jetson Thor
2070 TOPS · Module
MIXED25.029.5721 tok/s99.296.81,817Community
N
NVIDIA Jetson AGX Orin
275 TOPS · Module
MIXED35.943.8502 tok/s99.140.01,817Community
H
Hailo-8
26 TOPS · M.2
Not supported
H
Hailo-10H
40 TOPS · M.2
Not supported
Q
Qualcomm QCS6490
12 TOPS · SoC
Not supported
Q
Qualcomm QCS8550
48 TOPS · SoC
Not supported
Q
Snapdragon 8 Gen 3 NPU
45 TOPS · SoC
Not supported
N
NVIDIA Jetson Orin Nano
40 TOPS · SoM
Not supported
π
Raspberry Pi 5 + Hailo HAT
26 TOPS · HAT
Not supported
A
Ambarella CV5
16 TOPS · SoC
Not supported
A
Ambarella CV72
32 TOPS · SoC
Not supported
M
MediaTek Genio 700
4 TOPS · SoC
Not supported
G
Google Coral Edge TPU
4 TOPS · USB
Not supported
I
Intel Movidius Myriad X
4 TOPS · SoC
Not supported
A
AMD Versal AI Edge VE2302
22 TOPS · SoC
Not supported
Apple Neural Engine (M4)
38 TOPS · SoC
Not supported
R
Rockchip RK3588
6 TOPS · SoC
Not supported
Leader per columnOpenX-Embodiment · pick-and-place · 30 Hz target

HIL conditions

All numbers measured on Fo’c’sle HIL rigs in Tel Aviv (primary), Munich (secondary), and Pittsburgh (robotics). Single-stream, batch-1, real preprocessing, real downstream consumer. p50/p95 are over 10,000-frame steady-state windows after a 30-second warm-up. Power draw is package power, not wall power. Memory footprint is the resident model + activations footprint at peak — not on-disk.

Submitted publisher numbers are accepted only if they reproduce within ±8% of an HIL-lab matched run on the same chip in the same input mode. Otherwise they live separately under the Discussion tab.